A conventional option selection circuit, as shown in FIG. 1, includes a power source (VDD) connected to terminals on one side of a set of switches (S.sub.1 -S.sub.n) and a power source (VSS) connected to the opposite terminals on the other side of the switches S.sub.1 -S.sub.n). The common terminals of the switches (S.sub.1 -S.sub.n) are connected to inputs I.sub.1 -I.sub.n) of a binary coder (1). When a user selectively switches on the power source (VDD) or (VSS), the inputs of the binary decoder (1) are applied with a "high level" (=VDD) or a "low level" (=VSS) respectively so that the corresponding outputs make an option selection.
In FIG. 2 a conventional sequence selection circuit is arranged so that the outputs of each of the flip flops are connected to the inputs of the subsequent flip flip and the connection nodes between the outputs and the clock terminals of the flip flops (F.sub.1 -F.sub.n) are connected to the corresponding inputs of the binary decoder (1). Sequential clock pulse inputs to the flip flops develop outputs in the order of 000-000 , 000-001, 000-010 which are supplied to the inputs of the binary decoder (1). Accordingly, the outputs of the binary decoder (1) are developed in a sequential order for making a sequence selection.
In FIG. 3, a conventional combination circuit includes an option selection circuit as shown in FIG. 1 and a sequence selection circuit as shown in FIG. 2. In this conventional combination circuit, a clock pulse is applied to a flip flop (F.sub.1), the inverse output (Q.sub.1) of the flip flop and the output of inverter (I.sub.1) are connected to a NAND gate (N.sub.1), the output of the NAND gate (N.sub.1) is connected to a NAND gate (N.sub.2) via a flip flop (F.sub.2) and an inverter (I.sub.2), the output of the NAND gate (N.sub.2) is connected to a NAND gate (N.sub.3) via a flip flop (F.sub.3) and an inverter (I.sub.3). The connections continue in the same manner as described above in order to form a synchronous binary counter (3) of flip flops (F.sub.1 -F.sub.n), inverters (I.sub.1 -I.sub.n+1) and NAND gates (N.sub.1 -N.sub.n-1). The outputs (Q.sub.1 -Q.sub.n) of the flip flops (F.sub.1 -F.sub.n) are respectively connected to corresponding inputs of the binary decoder (1) and the common terminals of a set of switches (S.sub.1 -S.sub.n). The set of switches (S.sub.1 -S.sub.n) are so arranged that the terminals on one side are connected to a power supply (VDD) while the terminals on the other side are connected to a power supply (VSS). The flip flip (F.sub.1) includes a main flip flop (4), a slave flip flop (5) and an inverter (I.sub.n) as shown in FIG. 4.
In the circuit described above, an option selection causes the set of switches (S.sub.1 -S.sub.n) to apply inputs to the binary decoder for execution while a sequence selection causes the set of switches (S.sub.1 -S.sub.n) to be set to a "low level" state (=VSS) and presets all of the flip flops so that the synchronous binary counter (3) performs binary counting in response to the application of the clock pulse. The binary counting is given to the inputs of the decoder (1) for being output at the sequential outputs.